DK-DEV-5SGXEA7N【PDF 158/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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6-2

SERDES and DPA Bank Locations in Stratix V Devices

SV51007

2014.01.10

? DPA

? Synchronizer (FIFO buffer)

? Phase-locked loops (PLLs)

SERDES and DPA Bank Locations in Stratix V Devices

The dedicated serializer/deserializer (SERDES) and DPA circuitry that supports high-speed differential I/Os

is located in the top and bottom banks of the Stratix V devices.

Figure 6-2: High-Speed Differential I/Os with DPA Locations in Stratix V Devices

General Purpose I/O and High-Speed

Left Clock

Region

Right Clock

Region

LVDS I/O with DPA and Soft-CDR

Fractional PLL

Transceiver Block

FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

Left Clock

Region

Right Clock

Region

Related Information

PLLs and Clocking for Stratix V Devices on page 6-8

LVDS SERDES Circuitry

The Stratix V devices have built-in serializer/deserializer (SERDES) circuitry that supports high-speed LVDS

interfaces. You can configure the SERDES circuitry to support source-synchronous communication protocols

such as RapidIO ? , XSBI, serial peripheral interface (SPI), and asynchronous protocols such as Gigabit

Ethernet (GbE) and SGMII.

The following figure shows a transmitter and receiver block diagram for the LVDS SERDES circuitry with

the interface signals of the transmitter and receiver data paths.

Altera Corporation

High-Speed Differential I/O Interfaces and DPA in Stratix V Devices

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